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Digital Design
RTL DESIGN
- HDL coding
- System Verilog
- Verilog
DESIGN VERIFICATION
- Test Bench Development
- RTL Level Simulation
- Gate Level Simulation
- Functional Verification of Sub-Systems
SYNTHESIS
- Single Pass Synthesis (WLM based)
- Multi Pass Synthesis for lower nodes
- Timing Constraint Development (sdc)
- Power Domain Constraint Development (upf /
cpf)
- Low Power Optimization
- DFT Insertion
- MCMM
FLOOR PLANNING
- Floor planning as per the Design
requirements
- Port / Pin placement
- Macro, IP and Memory placement
POWER PLANNING
- Power Structure creation
requirements
- Primary, Secondary Power creation
- Power domains and Voltage Areas
STANDARD CELL PLACEMENT
- Placement of standard cells
- Congestion Analysis
- Global Route
- Scan Chain Routing optimization at Physical
Level
- Clock Aware Placement
CLOCK TREE SYNTHESIS
- Clock Spec creation
- Different modes of clock tree synthesis
- Clock Tree Optimization
- Clock path analysis for cost functions
ROUTING
- Track Route
- Detailed Route
RC EXTRACTION
- SPEF generation for blocks
- SPEF stitching for Top Level
POST ROUTE CHECKS
- Check for Antenna
- Standard Cell Filler cells
- Metal Fill
- CAA Checks
STATIC TIMING ANALYSIS
- Timing Analysis across multiple scenarios
(Modes + PVTRCs)
- Non-Functional ECO cycles
- Power vs Timing optimization
FORMAL VERIFICATION
- Block Level and Top Level Logic Equivalence
Check
IR / EM ANALYSIS
- Cross Optimization on IR and Timing
- Resistance Checks
PHYSICAL VERIFICATION
- Design Rule Checks
- Layout Versus Schematic
Analog Design
AUDIO IC DESIGN
- Pre-Amplifier
- Sigma-Delta Converter
POWER MANAGEMENT IC DESIGN
- DC-DC Converter
- Linear Drivers (AC-DC)
- SMPS
COMMUNICATION
- Bluetooth 4.0 PHY
- Bluetooth 4.2
RF DESIGN
- RF Design
- RF Board Design